A conventional package structure 200 as illustrated in FIG. 6 includes a substrate 210, a chip 220 and a plurality of solders 230, wherein the substrate 210 comprises a plurality of connection pads 211, and the chip 220 comprises a plurality of bumps 221. The solders 230 are applied to the bumps 221. The substrate 210 and the chip 220 are both laminated to make the bumps 221 electrically connected to the connection pads 211 via the solders 230. With the volume of present electronic products going into miniaturization, the spacing between each bump 221 and each connection pad 211 becomes relatively miniaturized. In this condition, the solders 230 likely flow to adjacent bump 221 or adjacent connection pad 211 to lead short phenomenon in the process of reflowing therefore lowering product yield rate.